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ADM1172
CIRCUIT BREAKER TIMING CYCLE
When the voltage across the sense resistor exceeds the circuit
breaker trip voltage, the 60 μA timer pull-up current is activated.
If the sense voltage falls below this level before the TIMER pin
reaches 1.3 V, the 60 μA pull-up is disabled and the 2 μA pull-
down is enabled. This is likely to happen if the overcurrent fault
is only transient, such as an inrush current. This is shown in
Figure 39. However, if the overcurrent condition is continuous
and the sense voltage remains above the circuit breaker trip
voltage, the 60 μA pull-up remains active. This allows the TIMER
pin to reach the high trip point of 1.3 V and initiate the GATE
shutdown. On the ADM1172-2 , the TIMER pin continues pulling
up but switches to the 5 μA pull-up when it reaches the 1.3 V
threshold. The device can be reset by toggling the ON-CLR pin
or by manually pulling the TIMER pin low. On the ADM1172-1 ,
the TIMER pin activates the 2 μA pull-down once the 1.3 V
threshold is reached, and continues to pull down until it reaches
the 0.2 V threshold. At this point, the 100 μA pull-down is
activated and the GATE pin is enabled. The device keeps
Data Sheet
AUTOMATIC RETRY OR LATCHED OFF
The ADM1172 is available in two models. The ADM1172-1
has an automatic retry system whereby when a current fault is
detected, the FET is shut down after a time determined by the
timer capacitor, and it is switched on again in a controlled con-
tinuous cycle to determine if the fault remains (see Figure 40
for details). The period of this cycle is determined by the timer
capacitor at a duty cycle of 3.8% on and 96.2% off.
The ADM1172-2 model has a latch off system whereby when a
current fault is detected, the GATE is switched off after a time
determined by the timer capacitor (see Figure 41 for details).
Toggling the ON-CLR pin, or pulling the TIMER pin to GND
for a brief period, resets this condition.
I RSENSE
5μA
retrying in the manner as shown in Figure 40.
The duty cycle of this automatic retry cycle is set to the ratio of
2 μA/60 μA, which approximates 3.8% on. The value of the
timer capacitor determines the on time of this cycle. This time
is calculated as follows:
t ON = 1.3 × C TIMER /60 μA
V TIMER
V GSFET
V OUT
60μA
SHORT-
CIRCUIT
EVENT
t OFF = 1.1 × C TIMER /2 μA
I RSENSE
2μA
V TIMER
60μA
100μA
V GSFET
COMP2
Figure 41. ADM1172-2 Latch Off After Overcurrent Fault
POWER-FAIL COMPARATOR
The ADM1172 has an integrated comparator that can be used
as a power-fail/OV/UV detector. The comparator has a 0.6 V
reference, and it is designed to be active high when the voltage
on the PFI pin drops to below this threshold. The only action
that results from the PFI pin tripping the comparator is the
change of state on the PFO pin. The PFI pin can be used to
V OUT
SHORT-
CIRCUIT
EVENT
monitor the supply on either side of the FET, for an OV or UV
condition set by a resistor divider network. The PFO can then
be sent to a control system and used as a power-good/power-fail
COMP2
FAULT
CYCLE
COMP1
FAULT
CYCLE
signal. The PFO output has a 5 μA internal pull-up. A 10 kΩ
resistor is recommended on the PFO pin to ensure that it is
Figure 40. ADM1172-1 Automatic Retry During Overcurrent Fault
either pulled up or down during power-up. The pin is in high
impedance while V CC < UVLO and can result in invalid power-
fail signals.
Rev. A | Page 14 of 16
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